The invention generally relates to a locked loop circuit, such as a delay locked loop circuit, for example.
For purposes of synchronizing operations of a particular circuit device with a system clock signal, the device may use a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit, a circuit that receives the system clock signal and generates a local clock signal that is synchronized to the system clock signal. Conventional PLL and DLL circuits consume significant die area and thus, as high performance semiconductor devices (central processing units (CPUs) and dynamic random access memory (DRAM) devices, for example) become increasingly more dense, challenges exist in placing the PLL and DLL circuits in these high performance devices. Furthermore, a digital system, such as a computer system, may have a large number of the PLL and DLL devices, thereby occupying a significant amount of die area in the overall system. For example, in a computer system, a CPU operates in synchronization with various other system devices, and therefore, synchronized clock signals must be generated inside the CPU, as well as inside the various devices that interact with the CPU.
PLL and DLL circuits have the capability of locking the phase of a generated clock signal to the phase of a given reference clock signal relatively independent of temperature, supply and manufacturing process variations. Therefore, these circuits have been the most popular solutions to synchronization problems. However, as noted above, these circuits may consume a significant amount of die area in a particular digital system. Furthermore, because the timing of the locked loop circuit is highly coupled to the process technology that is used to fabricate the locked loop circuit, the design of high performance locked loop circuits is a difficult task, thereby requiring significant design time.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.